/**
  ******************************************************************************
  * @file    _tc32l010_rcc.h
  * @author  CHIPAT Application Team
  * @brief   This file contains all the functions prototypes for the RCC 
  *          firmware library.
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __XS32L010_RCC_H
#define __XS32L010_RCC_H

#ifdef __cplusplus
 extern "C" {
#endif


#include "tc32l010.h"




/** @addtogroup tc32l010_StdPeriph_Driver
  * @{
  */

/** @addtogroup RCC
  * @{
  */

/* Exported types ------------------------------------------------------------*/

typedef struct
{
  uint32_t SYSCLK_Frequency;
  uint32_t HCLK_Frequency;
  uint32_t PCLK_Frequency;
  uint32_t ADCCLK_Frequency;
  uint32_t LPTIMCLK_Frequency;
  uint32_t LPUARTCLK_Frequency; 
}RCC_ClocksTypeDef;




/* Exported constants --------------------------------------------------------*/

/** @defgroup RCC_Exported_Constants
  * @{
  */

#define	RCC_SELECT_HSI_4M       0
#define	RCC_SELECT_HSI_16M      1
#define	RCC_SELECT_HSI_24M      2
#define	RCC_SELECT_LSI_32768    3

/** @defgroup RCC_HSE_configuration 
  * @{
  */

#define RCC_HSE_OFF                      ((uint8_t)0x00)
#define RCC_HSE_ON                       ((uint8_t)0x01)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON))

/**
  * @}
  */ 

#define RCC_HSE_CSS                       ((uint8_t)0x00)
#define RCC_LSE_CSS                       ((uint8_t)0x01)
#define IS_RCC_CSSON(CSS) (((CSS) == RCC_HSE_CSS) || ((CSS) == RCC_LSE_CSS))
  
#define IS_RCC_HSE_DETECTTIME(TIM)        (((TIM) > (uint8_t)0x00) && ((TIM) <= (uint8_t)0xFF))              

/** @defgroup RCC_HSI_Range 
  * @{
  */
#define RCC_HSIRANGE_4MHZ                 ((uint8_t)0x02)
#define RCC_HSIRANGE_16MHZ                ((uint8_t)0x01)
#define RCC_HSIRANGE_24MHZ                ((uint8_t)0x01)
#define IS_RCC_HSIRANGE(RANGE)           (((RANGE) == RCC_HSIRANGE_4MHZ) || \
                                          ((RANGE) == RCC_HSIRANGE_16MHZ)|| \
                                          ((RANGE) == RCC_HSIRANGE_24MHZ))

/**
  * @}
  */ 

/** @defgroup RCC_STABILIZATION_Clock_Source 
  * @{
  */

#define RCC_StabilizationSource_HSE                ((uint8_t)0x00) 
#define RCC_StabilizationSource_HSI                ((uint8_t)0x01) 
#define RCC_StabilizationSource_LSE                ((uint8_t)0x02)  
#define RCC_StabilizationSource_LSI                ((uint8_t)0x03) 

#define IS_RCC_STABILIZATION_SOURCE(SOURCE) (((SOURCE) == RCC_StabilizationSource_HSE)|| \
                                             ((SOURCE) == RCC_StabilizationSource_HSI)|| \
                                             ((SOURCE) == RCC_StabilizationSource_LSI))

#define RCC_StabilizationTime_4_256CYC           ((uint8_t)0x00) 
#define RCC_StabilizationTime_16_1024CYC         ((uint8_t)0x01) 
#define RCC_StabilizationTime_64_4096CYC         ((uint8_t)0x02) 
#define RCC_StabilizationTime_256_16384CYC       ((uint8_t)0x03) 

#define IS_RCC_STABILIZATION_TIME(TIME) (((TIME) == RCC_StabilizationTime_4_256CYC)  || \
                                         ((TIME) == RCC_StabilizationTime_16_1024CYC)|| \
                                         ((TIME) == RCC_StabilizationTime_64_4096CYC)|| \
                                         ((TIME) == RCC_StabilizationTime_256_16384CYC))

/**
  * @}
  */ 
  

/**
  * @}
  */

 
/** @defgroup RCC_System_Clock_Source 
  * @{
  */

#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
#define RCC_SYSCLKSource_LSI             RCC_CFGR_SW_LSI 
#define RCC_SYSCLKSource_LSE             RCC_CFGR_SW_LSE 

#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_HSE)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSI)   || \
                                      ((SOURCE) == RCC_SYSCLKSource_LSE))
/**
  * @}
  */

/** @defgroup RCC_AHB_Clock_Source
  * @{
  */

#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
                           ((HCLK) == RCC_SYSCLK_Div128))
/**
  * @}
  */ 

/** @defgroup RCC_APB_Clock_Source
  * @{
  */

#define RCC_HCLK_Div1                    ((uint8_t)0x00)
#define RCC_HCLK_Div2                    ((uint8_t)0x01)
#define RCC_HCLK_Div4                    ((uint8_t)0x02)
#define RCC_HCLK_Div8                    ((uint8_t)0x03)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) )
/**
  * @}
  */

  
/** @defgroup RCC_ADC_clock_source 
  * @{
  */
/* These defines are obsolete and kept for legacy purpose only.
Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
#define RCC_ADCCLK_Div1                 RCC_CFGR_ADCPRE_DIV1
#define RCC_ADCCLK_Div2                 RCC_CFGR_ADCPRE_DIV2
#define RCC_ADCCLK_Div4                 RCC_CFGR_ADCPRE_DIV4
#define RCC_ADCCLK_Div8                 RCC_CFGR_ADCPRE_DIV8

#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_Div1) || ((ADCCLK) == RCC_ADCCLK_Div2) || \
                               ((ADCCLK) == RCC_ADCCLK_Div4) || ((ADCCLK) == RCC_ADCCLK_Div8))
                           
/**
  * @}
  */

/**
  * @}
  */
/** @defgroup RCC_LPTIM_clock_source 
  * @{
  */

#define RCC_LPTIMCLK_PCLK                  RCC_CFGR_LPTIMSEL_PCLK
#define RCC_LPTIMCLK_LSI                   RCC_CFGR_LPTIMSEL_LSI
#define RCC_LPTIMCLK_LSE                   RCC_CFGR_LPTIMSEL_LSE

#define IS_RCC_LPTIMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_LPTIMCLK_PCLK)  || \
                                        ((SOURCE) == RCC_LPTIMCLK_LSI)   || \
                                        ((SOURCE) == RCC_LPTIMCLK_LSE))

/**
  * @}
  */
  
/** @defgroup RCC_LPUART_clock_source 
  * @{
  */

#define RCC_LPUARTCLK_PCLK                  RCC_CFGR_LPUARTSEL_PCLK
#define RCC_LPUARTCLK_LSI                   RCC_CFGR_LPUARTSEL_LSI
#define RCC_LPUARTCLK_LSE                   RCC_CFGR_LPUARTSEL_LSE

#define IS_RCC_LPUARTCLK_SOURCE(SOURCE)  (((SOURCE) == RCC_LPUARTCLK_PCLK)  || \
                                          ((SOURCE) == RCC_LPUARTCLK_LSI)   || \
                                          ((SOURCE) == RCC_LPUARTCLK_LSE))

/**
  * @}
  */
         
/** @defgroup RCC_Interrupt_Source 
  * @{
  */
#define RCC_IT_CSSLSE                    ((uint8_t)0x01)
#define RCC_IT_CSSHSE                    ((uint8_t)0x02)

#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))

#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_CSSLSE) || ((IT) == RCC_IT_CSSHSE))

#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)

/**
  * @}
  */
  
/** @defgroup RCC_LSE_Configuration 
  * @{
  */

#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
#define RCC_LSE_ON                       RCC_LCSR_LSEON
#define IS_RCC_LSE(LSE)     (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON))
/**
  * @}
  */

/** @defgroup RCC_RTC_Clock_Source
  * @{
  */
#define RCC_RTCCLKSource_LSE             RCC_LCSR_RTCSEL_LSE
#define RCC_RTCCLKSource_LSI             RCC_LCSR_RTCSEL_LSI
#define RCC_RTCCLKSource_HSE_NONE        ((uint32_t)0x00000001)
#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00130001)
#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00230001)
#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00330001)
#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x00430001)
#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x00530001)
#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00630001)
#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00730001)

#define IS_RCC_RTCCLK_SOURCE(SOURCE) ((SOURCE) == RCC_RTCCLKSource_LSE || \
                                      (SOURCE) == RCC_RTCCLKSource_LSI) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_NONE) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24))
/**
  * @}
  */

  
/** @defgroup RCC_AHB_Peripherals 
  * @{
  */
#define RCC_AHBPeriph_FLASH               RCC_AHBENR_FLASHEN
#define RCC_AHBPeriph_STCKEN              RCC_AHBENR_STCKEN
#define RCC_AHBPeriph_DMA                 RCC_AHBENR_DMAEN
#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN

#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0x00FFFFFF) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0x40FFFFFF) == 0x00) && ((PERIPH) != 0x00))

/**
  * @}
  */

/** @defgroup RCC_APB_Peripherals 
  * @{
  */
#define RCC_APBPeriph_USART0            RCC_APBENR_USART0EN
#define RCC_APBPeriph_USART1            RCC_APBENR_USART1EN
#define RCC_APBPeriph_SPI0              RCC_APBENR_SPIEN
#define RCC_APBPeriph_I2C0              RCC_APBENR_I2CEN
#define RCC_APBPeriph_TIM1              RCC_APBENR_TIM1EN
#define RCC_APBPeriph_PCA               RCC_APBENR_TIM3EN
#define RCC_APBPeriph_TIM4              RCC_APBENR_TIM4EN
#define RCC_APBPeriph_TIM5              RCC_APBENR_TIM5EN
#define RCC_APBPeriph_SYSCFG            RCC_APBENR_SYSCFGEN  
#define RCC_APBPeriph_WWDG              RCC_APBENR_WWDGEN  
#define RCC_APBPeriph_IWDG              RCC_APBENR_IWDGEN 
#define RCC_APBPeriph_RTC               RCC_APBENR_RTCEN
#define RCC_APBPeriph_ADC               RCC_APBENR_ADCEN
#define RCC_APBPeriph_TIM2              RCC_APBENR_TIM2EN 
#define RCC_APBPeriph_PWR               RCC_APBENR_PWREN  
#define RCC_APBPeriph_LPTIM0            RCC_APBENR_LPTIMEN
#define RCC_APBPeriph_LPUART0           RCC_APBENR_LPUARTEN


#define IS_RCC_APB_PERIPH(PERIPH) ((((PERIPH) & 0xFFF0E000) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_APB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFFF0EC00) == 0x00) && ((PERIPH) != 0x00))
/**
  * @}
  */ 

/** @defgroup RCC_APB1_Peripherals 
  * @{
  */

/**
  * @}
  */

/** @defgroup RCC_MCO_Clock_Source
  * @{
  */

#define RCC_MCOSource_NoClock            RCC_CFGR_MCOSEL_NOCLK
#define RCC_MCOSource_SYSCLK             RCC_CFGR_MCOSEL_SYSCLK
#define RCC_MCOSource_HSI                RCC_CFGR_MCOSEL_HSI
#define RCC_MCOSource_HSE                RCC_CFGR_MCOSEL_HSE
#define RCC_MCOSource_LSI                RCC_CFGR_MCOSEL_LSI
#define RCC_MCOSource_LSE                RCC_CFGR_MCOSEL_LSE

#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
                                   ((SOURCE) == RCC_MCOSource_HSI)     || ((SOURCE) == RCC_MCOSource_HSE)    || \
                                   ((SOURCE) == RCC_MCOSource_LSI)     || ((SOURCE) == RCC_MCOSource_LSE))
/**
  * @}
  */ 

/** @defgroup RCC_MCOPrescaler
  * @{
  */

#define RCC_MCOPrescaler_1            RCC_CFGR_MCOPRE_DIV1
#define RCC_MCOPrescaler_2            RCC_CFGR_MCOPRE_DIV2
#define RCC_MCOPrescaler_4            RCC_CFGR_MCOPRE_DIV4
#define RCC_MCOPrescaler_8            RCC_CFGR_MCOPRE_DIV8

#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_2)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_4)  || \
                                         ((PRESCALER) == RCC_MCOPrescaler_8))
                                   
/**
  * @}
  */ 

/** @defgroup RCC_Flag 
  * @{
  */
#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
#define RCC_FLAG_HSERDY                  ((uint8_t)0x09)
#define RCC_FLAG_LSIRDY                  ((uint8_t)0x21)
#define RCC_FLAG_LSERDY                  ((uint8_t)0x29)
#define RCC_FLAG_PORRSTF                 ((uint8_t)0x40)
#define RCC_FLAG_SFTRSTF                 ((uint8_t)0x41)
#define RCC_FLAG_WWDGRSTF                ((uint8_t)0x42)
#define RCC_FLAG_LOCKUPRSTF              ((uint8_t)0x43)
#define RCC_FLAG_PINRSTF                 ((uint8_t)0x44)
#define RCC_FLAG_IWDGRSTF                ((uint8_t)0x45)
#define RCC_FLAG_LVDRSTF                 ((uint8_t)0x46)

#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)   || ((FLAG) == RCC_FLAG_HSERDY)  || \
                           ((FLAG) == RCC_FLAG_LSIRDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \
                           ((FLAG) == RCC_FLAG_PORRSTF)  || ((FLAG) == RCC_FLAG_SFTRSTF) || \
                           ((FLAG) == RCC_FLAG_WWDGRSTF) || ((FLAG) == RCC_FLAG_LOCKUPRSTF) ||\
                           ((FLAG) == RCC_FLAG_PINRSTF)  || ((FLAG) == RCC_FLAG_IWDGRSTF) || \
                           ((FLAG) == RCC_FLAG_LVDRSTF))

#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)

#define IS_RCC_LSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
#define IS_RCC_LSI_TRIMMING_VALUE(VALUE) ((VALUE) <= 0xF)

/**
  * @}
  */

/**
  * @}
  */

/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

/* Function used to set the RCC clock configuration to the default reset state */
void RCC_DeInit(void);

/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_SetHSIRange(uint8_t HSIRange);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue, uint8_t HSITrimmingValue);
void RCC_AdjustLSICalibrationValue(uint8_t LSICalibrationValue, uint8_t LSITrimmingValue);
void RCC_SetClockStabilizationTime(uint8_t RCC_CLKSource, uint8_t RCC_Time);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint32_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(uint32_t RCC_Source, FunctionalState NewState);
void RCC_ClockSecuritySystemDetectTimSet(uint8_t HSI_ClkNum);
void RCC_MCOConfig(uint32_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
void RCC_SET_TrimValue(uint32_t source);

/* System, AHB and APB busses clocks configuration functions ******************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLKConfig(uint32_t RCC_HCLK);
void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete.
                                               For proper ADC clock selection, refer to
                                               ADC_ClockModeConfig() in the ADC driver */

void RCC_LPTIMCLKConfig(uint32_t RCC_LPTIMSource);
void RCC_LPUARTCLKConfig(uint32_t RCC_LPUARTSource);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);

/* Peripheral clocks configuration functions **********************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_RTCResetCmd(FunctionalState NewState);

void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APBPeriphClockCmd(uint32_t RCC_APBPeriph, FunctionalState NewState);

void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APBPeriphResetCmd(uint32_t RCC_APBPeriph, FunctionalState NewState);

/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);

  
#ifdef __cplusplus
}
#endif

#endif /* __XS32L010_RCC_H */

/************************ (C) COPYRIGHT CHIPAT *****END OF FILE****/
